1. Technical Field
The present invention relates to techniques for establishing connections for three-dimensional integrated circuits and, in particular, to suppressing substrate noise coupling due to currents on through silicon vias in a three-dimensional integrated circuit.
2. Description of the Related Art
Through silicon via technology (TSV) enables vertical connections for three-dimensional stacked integrated circuits (ICs) and silicon packages. A significant advantage of using TSVs is their small form factor, allowing higher density input/output placement and thereby making possible higher bandwidth and lower-power signaling. Due to the dense distribution of TSVs, however, TSV noise coupling is a significant concern for three-dimensional IC system design, particularly in sensitive applications such as phase-locked loops. Although TSVs are often coated with a dielectric liner to avoid direct current contact to the substrate, thin dielectric layers may not be effective to prevent high-frequency noise penetrating into the substrate.
A circuit is shown that includes a substrate; a conductive layer on the first side of the substrate; a device component above the conductive layer; and a buried interface tie. The substrate includes a through via that provides access to components on a first side of the substrate to components on a second side of the substrate; and a ground via. The buried interface tie is in contact with the conductive layer and connected to the ground via, disposed adjacent to the device component to isolate the device component from coupling noise.
Conventional noise shielding in two-dimensional ICs often use a guard ring structure. The principle of a guard ring is to create a low-impedance path to the ground to capture the substrate coupling noise. In order to achieve effective noise suppression, a guard ring in a three-dimensional IC needs a large width as well as a large separation distance between TSV and the ring. This sacrifices active circuit area and reduces wiring flexibility near the TSV. Furthermore, such guard rings are intended for bulk silicon and the design is not directly applicable to silicon-on-insulator technologies.